1. Field of the Present Invention
The present invention relates to the field of integrated circuit design and more particularly to the field of integrated circuit design verification systems.
2. History of Related Art
As the complexity of microprocessors and other large scale integrated circuits has increased over the years, the resources devoted to design verification have accounted for an increasingly large percentage of the total resources required to develop and manufacture such a device. Indeed, verifying the proper furtherality of advanced microprocessors having multiprocessing capability is now estimated to consume more time, labor, and other resources than the actual designing of the device.
Historically, functional verification consisted primarily of generating large numbers of test programs or test cases and running those test programs on a simulator that modeled the device operation. Designers and verification engineers frequently developed such test cases manually with the help of various random and specific test generators. As the number of transistors, furthers, registers, and other facilities in the integrated circuit has increased, conventional verification methods have responded by simply increasing the number of tests that are simulated. Unfortunately, generating a seemingly infinite number of tests is an inefficient and unreliable method of verifying the functionality of all components in a complex circuit.
In the early days of microprocessor development, inefficiencies in functional verification systems were tolerated because the size of the test space (measured, for example, by the number of states the microprocessor may assume) was sufficiently small. In addition, early microprocessors typically had fewer functional units than modern microprocessors, and the interactions between the components and functions were well understood and controlled. The increasing number of functional units in microprocessors is significant from a verification perspective because interaction between functional units can no longer be ignored or only loosely verified by conventional verification methodologies.
The diverse applications in which modern integrated circuits are employed makes it impossible to predict and plan for the type of software applications that will run on them and thus the state and interdependence that will be exercised in the field are rather large and generally non-deterministic. Roughly speaking, the test space of a microprocessor is approximately equal to 2n where n represents the number of latches (state storage devices) within the microprocessor. From this approximation, it will be appreciated that the test space of microprocessors increases exponentially as the number of latches is increased.
The conventional approach to functional verification, in which increased complexity in a device is verified by simply increasing the number of tests that are simulated, is rapidly becoming infeasible. In addition, because the input to a simulator in a conventional verification process is simply a large number of deterministic tests or randomly generated tests, the output of the simulation must be painstakingly evaluated to determine whether a particular simulation was successful in testing the intended functionality of the device.
Adding to the cost and time required to perform functional verification are the inevitable design modifications that are made during the design process. The design of a complex integrated circuit typically evolves many times during its development as new functionality is entered, as design flaws are rectified, as synthesis optimizations are performed on the design to meet timing/size constraints, and as pervasive functions such as test logic are added. Regardless of how small a change is, it is typically necessary to perform the verification process anew every time the design changes unless the change is demonstrated to be extremely trivial. The time required to re-verify a design is particularly limiting when the design change necessitating the re-verification occurs near the end of the design phase (i.e., close to “tape out”, “first silicon”, or any other significant step in the completion of the design).
It would therefore be desirable to implement a test verification system that addressed the design verification noted above.